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Baldin, Daniel: Reconfiguration of legacy software artifacts in resource constraint embedded systems. 2014
Inhalt
Abstract
Zusammenfassung
Acknowledgments
Contents
List of Figures
List of Tables
Listings
Acronyms
Foundation
1 Introduction
1.1 Motivation
1.2 Goal of the Thesis
1.3 Thesis Contributions
1.4 Thesis Outline
2 Basics
2.1 Smart-Card SOC
2.2 Object Files
2.3 The ELF Object File Format
2.4 Program Representation
2.4.1 Control Flow Graph
2.4.2 Call Graph
2.5 Data Flow Analysis
2.5.1 Data Flow Analysis Equations
2.5.2 Data Flow Problems
2.6 Contexts
2.6.1 Graphs with Context
2.6.2 Example
2.7 Summary
3 Related Work
3.1 Binary Analysis Approaches
3.1.1 Link-Time Optimization
3.1.2 Problems solved by Binary Analysis
3.2 Program Analysis Problems
3.2.1 Code Discovery
3.2.2 Self modifying code
3.2.3 Indirect Control Flow Target Detection
3.2.4 Detecting Idioms
3.3 Tools
3.3.1 Binary Decoding
3.4 Reconfigurable/Adaptable Systems
3.4.1 Structural Reconfiguration Mechanisms
3.5 Conclusion
The Approach
4 Legacy Code Reconfiguration
4.1 Requirements
4.2 Methodology
4.3 Consistency Preservation
4.3.1 Integrity
4.3.2 Consistency
4.3.3 State-Invariant
4.4 Architecture Restrictions of this Thesis
4.5 Open Problems
5 Control Flow Reconstruction
5.1 Building the Control Flow Graph
5.1.1 Interprocedural Control Flow Graph
5.1.2 Basic Block Augmentation
5.1.3 Indirect Control Flow Target Resolution
5.1.4 Safe Over-approximation
5.2 Summary
6 Component Model
6.1 Defining Reconfiguration Components
6.2 Reconstructing the Application Semantics
6.3 Generating the High-Level Annotated Control Flow Graph
6.3.1 High Level Expression Detection and Normalization
6.3.2 Memory Access Patterns
6.3.3 Arithmetic and Binary Patterns
6.3.4 High Level Variable Substitution
6.3.5 Global Variable Detection
6.4 Constraint-based Component Identification
6.5 Ensuring Disjoint Components
6.6 Summary
7 Runtime Reconfiguration
7.1 The Reconfiguration Architecture
7.2 The Reconfiguration Protocol
7.3 Reconfiguration Activities
7.3.1 Memory Management
7.3.2 Replacement Strategy
7.3.3 Indirection Layer
7.4 Operating System Integration
7.5 Real Time Characteristics
7.6 Summary
8 Component Optimization
8.1 Target System Restrictions / Notation
8.2 Optimization Steps
8.2.1 Component Partitioning
8.2.2 Component Merging
8.3 Calculating the Worst Case Blocking Time
8.3.1 Efficient WCET Calculation by Path Enumeration
8.3.2 Handling Cyclic Reconfigurations
8.3.3 Speedup of the Algorithm
8.3.4 Quality of the Estimation
8.4 Design Space Exploration
8.5 Summary
9 Binary Transformation
9.1 Modification Flow
9.2 ELF File Modification
9.2.1 Instrumentation Code
9.2.2 Data Duplication
9.2.3 Additional Linker Symbols
9.3 Summary
Evaluation
10 Evaluation
10.1 Case Study - SmartCard IPStack
10.1.1 Design Time Overhead
10.1.2 Reconfiguration Manager Binary Overhead
10.1.3 Component Extraction
10.1.4 Reconfiguration Delay Function
10.2 Design Space Exploration
10.3 Summary
11 Conclusion and Future Work
11.1 Thesis Summary
11.2 Outlook
Appendix
A Appendix
A.1 Mathematical Notation
A.2 Additional Path Enumeration Considerations
A.3 Calling Convention (RC_ABI)
A.4 System Constraint Language ABNF
A.5 Evaluation Design Points
A.6 The ARMv4(t) ISA
Bibliography
Declaration
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